1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and, more particularly, to a differential cell-type EPROM incorporating a stress test circuit.
2. Description of the Related Art
A read-only memory of a type whose data can be erased by means of an ultraviolet ray so as to enable data rewrite, i.e., a so-called EPROM, is widely known by, e.g., U.S. Pat. Nos. 3,660,819 (1972), 3,744,036 (1973), and 3,755,721 (1973).
In the EPROM, when a memory cell (cell transistor) is selected to write data, a word line and a bit line connected to this memory cell are set at a high potential. Then, a high potential is also applied to the drain or control gate of non-selected memory cells connected to the same word line and bit line of the selected memory cell, and electrons charged in the floating gate are sometimes discharged due to the stress applied to the drain o control gate of the non-selected memory cells. As a result, stored data is inverted, causing problems.
In order to evaluate data retaining characteristics of an EPROM, a reliability test such as a drain stress test and a gate stress test is performed by forcibly giving stress to the drains or control gates of the memory cells. In the drain stress test, a high potential is applied to the gates of all the column selecting transistors in order to turn on these transistors. In this case, when a write transistor is turned off, the drains of all the column selecting transistors are set at 0 V. Then, stress can be given to the gate insulating films of the column selecting transistors. Therefore, the stress test for the column selecting transistors is often performed in addition to the drain stress test. The gate stress test and the stress test for the column selecting transistors are common in that both tests are performed by turning off the write transistor. Therefore, these two tests can be simultaneously performed by selecting all the word lines.
In the stress test, since stress must be given to the drains or control gates of all the memory cells, the time required for testing is prolonged as the memory capacity is increased. In order to shorten the test time, e.g., U.K. Patent Application No. GB2,053,611 published (Feb. 4, 1981) by Vernon George McKenney et al. proposes to incorporate in an EPROM a stress test circuit having a function of performing the stress as described above on the memory cells.
Recent technology trends require high speed operation for an EPROM as well as other memory devices. Various methods are available to realize a short access time. Among those methods, a differential cell method is known. Basically, the differential cell method uses two cell transistors to constitute a single memory cell (in other words, 1-bit data is stored using two cell transistors). Complementary data are written in two cell transistors. Readout potentials from the two cell transistors are input to a differential amplifier, thereby amplifying the difference and thus reading out stored data. This differential cell-type EPROM is described in, e.g., "A 25ns 16K CMOS PROM using a 4-Transistor Cell" by Saroj Pathak et al. in 1985 IEEE International Solid-State Circuits Conference DIGEST OF THE TECHNICAL PAPERS, pp. 162, 163 and in U.S. Pat. No. 4,970,691 (1990) by the present inventors.
However, in the differential cell-type EPROM, if a stress test for a single end cell-type EPROM in which a single transistor memory cell is employed, the time required for the drain stress test may be doubled, or the write transistor may be broken during the gate stress test. These problems arise because two write transistors corresponding to two memory cell arrays are complementarily turned on/off (i.e., only one of the write transistors can be turned on). As a result, the stress test for the drain and/or the column selecting transistor must be separately performed for two memory cell arrays, thus doubling the test time. When the gate stress test is to be performed, or the gate stress test and the stress test for the column selecting transistors are to be simultaneously performed, the write transistor must be turned off. In the differential cell-type EPROM, one of the two write transistors is turned on and the remaining one is turned off, as described above. As a result, a high potential is applied to the gate and drain of the write transistor which is in an ON state, and the source is substantially at 0 V. Then, a stress is applied to the gate insulating film of this transistor, resulting in breakdown.